In a random NRZ data signal, data are represented by a constant signal level for the full duration of a bit interval, i.e. one clock cycle. For example, an NRZ data signal is shown in FIG. 1. In NRZ type signals, a high signal level during a bit interval indicates a logic one, while a low signal level during a bit interval indicates a logic zero. NRZ data signals are preferred, due to their simplicity in generation. By contrast, RZ (return-to-zero) data signals return to zero during each bit interval, thereby requiring a greater frequency to transmit identical information contained in an NRZ data signal.
If a clock signal such as that shown in FIG. 1 is used to trigger the horizontal sweep of an oscilloscope and an NRZ data signal is applied to the vertical channel of such an oscilloscope, a distinctive pattern known as an eye diagram will appear. Such an eye diagram is shown for the input data signal in FIG. 1. When data is received and depicted on an oscilloscope in this fashion, multiple transitions of the data are superimposed, thereby defining each bit or clock period. In order to insure maximum reliability when sampling NRZ data signals, it is desirable to sample such signals at the midpoint of each bit interval. As shown in FIG. 1, utilization of the rising edge of the clock signal to sample the input data assures that sampling will occur at the midpoint of each eye pattern or bit interval. By sampling at such times, the input data can be regenerated.
Such regeneration is known to be desirable in transmission and communication systems in order to remove noise and other degradation of the data signal. If the clock signal assures sampling of the input data at the midpoint of each bit interval, an output data signal can be generated which when viewed on an oscilloscope will appear similar to the output eye diagram shown in FIG. 1. Since a clock signal is typically not transmitted with NRZ data signals, it will be necessary to recover the clock signal from the input data.
In the past, a number of techniques have been proposed for recovering the clock signal from a received data signal. These techniques can generally be divided into two classifications, namely, direct extraction techniques and phase locked loop techniques. In direct extraction techniques, typically the data signal is applied to a series arrangement including a non-linear detector, a high Q band pass filter and a limiter. The output of the limiter is used as the recovered clock signal.
One problem with direct extraction techniques, is their expense. Another problem associated with direct extraction techniques relates to performing clock extraction in circuitry which is independent from that circuitry used to retime data. Direct extraction techniques are generally not integrable. In such situations, it is not possible to control phase differences without the incorporation of additional compensating circuitry. Consequently, the phase differences which result from differences between the extraction and retiming circuitry are temperature dependent and will vary depending on the exact circuitry used. More common is the use of clock synthesis techniques.
In phase locked loop techniques, generally a local oscillator generates a clock signal which is compared to the incoming data stream in order to determine whether such clock signal is early or late in phase in relation to the data stream. Depending on whether the clock signal is early or late, the frequency of the local oscillator is adjusted higher or lower until the clock signal is determined to be in phase with the data signal.
U.S. Pat. No. 4,280,099--Rattlingourd discloses a digital timing recovery system for recovering a clock signal from NRZ data. In that system, an oscillator generates a local clock signal which is provided to a variable divider. The variable divider divides the oscillator signal by some integer amount and provides a clock output signal. The clock output signal is provided to a phase detector and compared with received NRZ data. The output of the phase detector is accumulated in a counter which in turn controls the integer used to divide the clock signal in the variable divider. As the integer is increased and decreased, the frequency of the clock signal generated by the variable divider will increase or decrease.
U.S. Pat. No. 4,371,974--Dugan discloses a digital phase detector for use with recovering clock pulses from received NRZ data. The phase detector is incorporated in a phase locked loop circuit. It is stated that the phase detector generates a phase error signal which is amplified and fed to a voltage controlled oscillator (VCO). The voltage controlled oscillator generates a clock signal having a frequency which is dependent upon the input voltage. The output of the voltage controlled oscillator is utilized by the phase detector for comparison with the received NRZ data.
The problem with such prior devices arises as data frequencies increase. As frequencies become higher, time delays inherent in digital devices become more significant in relation to the bit interval. As the bit interval becomes smaller, the time delay can assume a significant fractional portion of the bit interval, eventually preventing clock extraction and data retiming.
In addition, such prior phase locked loop techniques exhibit false lockup and jitter accumulation problems. False lock up can occur when the phase detector is implemented without prior knowledge of the data frequency characteristics. In such situations lock up tends to occur at small integer ratios of the data frequency, such as 4/5 ar 5/7 of the correct data frequency. Jitter accumulation is related to jitter gain, where jitter gain is the difference between the change in phase of the retimed data versus the change in phase of the original data. Ideally jitter gain is one (1). However, if a change in the input phase creates a larger change in the output phase a positive jitter gain results. In transmission and communication systems, where multiple clock extraction and retiming occur, jitter gain can accumulate exponentially from the beginning to the end of the system. Additionally, many traditional phase locked loop systems incorporate second order filters which can cause peaking of the jitter gain.
As is known, as jitter increases, the reliability and/or accurateness of sampling an incoming data signal decreases. Accordingly, other schemes and techniques have been proposed for clock extraction from NRZ data signals transmitted in the gigabit frequency range. Once such device is disclosed in "PHASE LOCKED LOOP OR CLOCK EXTRACTION IN GIGABIT RATE DATA COMMUNICATION LINKS," filed Nov. 18, 1988, and bearing Ser. No. 24,975, owned by the assignee of the present application. It is noted in that application that if a clock signal can be successfully extracted from the incoming data stream, such clock signal can then be used to sample the data stream, providing a regenerated data stream. However, that device was not capable of recovering a clock signal from purely random NRZ data. The clock recovery scheme disclosed in the application required the NRZ data to be grouped into fixed length frames prior to transmission. At the beginning of each frame, a master transition was provided. By locking on the frequency of the master transition signal, a local oscillator could be locked into generating a two gigabit clock signal, appropriate for use in sampling data. In addition, prior to data transmission a training signal was transmitted in order to facilitate locking of the clock signal.
Consequently, a need still exists for a device which can recover a clock signal from a random NRZ data signal which data signal is transmitted in the gigabit frequency range, which can retime data in relation to the recovered clock signal and which does not suffer from the problem of temperature effected, independent circuitry.